1. Field of the Invention
The present invention relates to a process for conducting wire and contact opening in semiconductor structure, more specifically, to a method for reducing photoresist thickness and via resistance in conducting wire process.
2. Description of the Prior Art
In manufacturing semiconductor devices such as DRAM, the process for forming conducting wires is very important.
A conventional process for forming conducting wires will be described with reference to FIG. 1.
First, a first dielectric layer 12 is formed on a semiconductor substrate 10. The first dielectric layer 12 is dug to form a via 14, and the via 14 is filled with metal. The resultant structure is shown in FIG. 1a. 
Then, on the first dielectric layer 12 comprising the via 14 filled with metal, a conductive layer 16 is formed. In practical process, the conductive layer 16 comprises a metal layer 160 of aluminum, aluminum/copper or any other suitable material, and thin Ti/TiN protective layers 162, 164 formed on the bottom and top of the metal layer 160, as shown in FIG. 1b. 
Subsequently, as shown in FIG. 1c, a photoresist layer comprising photoresist portions 182, 184 and 186 is formed on the structure of FIG. 1b, in order to remove undesired portions of the conductive layer 16 to form recesses 15, as shown in FIG. 1d. The remaining portions of the conductive layer 16 form conducting wires.
However, in the step of forming the photoresist layer, since the photoresist must have considerable thickness, the aspect ratio of certain photoresist portion is large. When the aspect ratio of the photoresist portion exceeds a certain degree, it intends to incline or even collapse, as indicated by the reference number 186′ in FIG. 1c′. If the photoresist portion inclines or collapses, the accuracy of the etched profile is degraded, causing the pattern consisting of the remaining metal portions after etching is different from the predetermined pattern.
In the subsequent process for forming a contact opening, a second dielectric layer 152 is formed to fill the recesses 15. Then, planarization is performed. A third dielectric layer 17 is formed on the entire structure, as shown in FIG. 1e. 
On the third dielectric layer 17, a photoresist layer 19 is formed, as shown in FIG. 1f. 
Finally, a contact opening 175 is opened by etching process, and the photoresist layer 19 is removed, as shown in FIG. 1g. However, in the etching process, the protective layer 164 of the conducting wire corresponding to the contact opening 175 is often undesirably etched off, resulting in the damage to the conducting wire, and causing the via resistance increases.
Therefore, a solution for solving the above problems is needed. The present invention satisfies such a need.